1. Field of the Invention
The present invention relates to a variable delay circuit, and more particularly to a variable delay circuit suitable for integration into a semiconductor memory device and capable of variably delaying an input signal by means of an OTA-C (operational transconductance amplifier-capacitor filter), when there occurs a change in a fabrication process or an input voltage.
2. Description of the Prior Art
Typically, as shown in FIG. 1, a conventional delay circuit in a conventional semiconductor memory device is composed of a plurality N of delay units (1-N) in series.
As shown in FIG. 2, each of the delay units includes: an inverter 10 for inverting an input signal IN1; an NMOS transistor 20 to the drain of which the output from the inverter 10 is applied through a resistance 15, to the gate of which the input signal IN1 is applied, and the source of which is connected to a ground voltage Vss potential; a PMOS transistor 25 configured as a capacitor and to the gate of which the drain of the NMOS transistor 20 is connected, and to the drain and source of which a supply voltage Vcc is applied; a NAND gate 30 for NANDing the output from the drain of the NMOS transistor 20 and a reset signal RST for thereby generating an output signal OT1; and a switch SW1 for switching a parallel shunt connection line also carrying the input signal IN1 and generating the output signal OT1.
With reference to FIGS. 3A and 3B, the operation of the thusly composed conventional delay circuit will now be described.
First, as shown in FIG. 3A, with switch SW1 opened (turned off) when the input signal IN1 transits from low to high, the inverter 10 inverts the transited high level signal to a low level. At the same time, the NMOS transistor 20, to the gate of which the input signal IN1 is applied, is turned on by the transited high signal IN1 and also discharges through the NMOS transistor 20 the supply voltage Vcc charged on the PMOS transistor capacitor 25 from the node N1, to ground Vss. As a result, the NAND gate 30 outputs a high level signal in accordance with the level at node N1 and the signal from the reset terminal RST.
Therefore, as shown in FIG. 3B, during the rising edge of the input signal IN1, the discharging of the PMOS transistor capacitor 25 is hurried through the NMOS transistor 20, thereby causing a certain time delay D1 with respect to the rising of output signal OT1. Conversely, during a falling edge of the input signal IN1, the NMOS transistor 20 is turned off according to the transited signal, and the inverter 10 inverts the low level input signal IN1 to a high level signal.
During the transition of the input signal IN1, the PMOS transistor 25 capacitor is discharged until the voltage at the node N1 reaches a high level, and the NAND gate 30 NANDs the high level signal at the node N1 and a high signal from the reset terminal RST, thereby outputting a low level output signal OT1.
So, during a rising edge of the input signal IN1, because the output signal OT1 depends on the RC time constant of the resistance 15 and the PMOS transistor capacitor 25 and thus requires a longer time to rise, the time delay D2 during a falling edge of the input signal IN1 remains longer than the time delay D1 during a rising edge of the input signal N1.
When a time delay is not required, the switch SW1 connected to the output of the NAND gate 30 is respectively closed (turned on), whereby the input signal is directly outputted without passing through the delay circuit.
However, the conventional delay circuit of the semiconductor memory device delays the input signal by using the resistance 15 and the PMOS transistor capacitor 25 which are respectively sensitive to the fabrication process and the supply voltage Vcc, thereby causing an instability in the delay time.
Particularly, for obtaining a longer delay time than 5 ns, more delay circuits had to be serially connected to each other, thereby causing difficulties in application to a highly integrated circuit.